Telecommunications devices such as network switches and routers typically include various line cards and switch cards mounted to a backplane and electrically interconnected through metal traces printed on the backplane. Due to the immense number of interconnections demanded by modern switching and routing applications, the present generation of backplane products are complex structures having as many as 40 or more metal layers. Such structures tend to be difficult to manufacture and expensive, as any small deviation from design specifications can render them useless.
FIG. 1 illustrates a prior-art backplane-based interconnection system 100 including a multi-layer backplane 101 and a pair of daughterboards 103A, 103B. To establish interconnections between the daughterboards 103A, 103B, metal traces 113 are printed on the various backplane layers and routed between respective via pairs (e.g. 111A, 111B). Metal pins 123 inserted in the vias form projecting contacts that extend from the backplane 101 into a connector socket 121. Each of the daughterboards 103A, 103B includes a printed circuit board (PCB) 119 and edge connector 105, the edge connector 105 having conductive receptacles 109 to receive the pins 123 projecting from the backplane 101. The receptacles 109 are electrically coupled to traces 117 within the PCB 119 by conductive members 107 which extend into trace-coupled vias 115. Ultimately, the PCB traces 117 extend to far-end vias which enable connection to contacts of an integrated circuit (IC) device (not shown), the IC device itself including an IC die (i.e., chip) disposed within an IC package and having signal routing paths that extend from package contacts to the chip. Thus, a signal transmitted over the interconnection system 100 passes from chip to package to PCB 119, through PCB trace 117 to connector 105, from the connector 105 to the backplane 101, through backplane trace 113 to another daughterboard connector at which the path back to the recipient chip is replicated in reverse.
The signaling bandwidth that can be achieved in the interconnection system 100 is limited by a number of factors. For example, various sources of impedance discontinuities (e.g., at the IC package interface and daughterboard connectors 105) reflect electrical energy back to the source, adding or subtracting from the incident signal and thereby increasing the noise to signal ratio. One of the most troublesome sources of impedance discontinuity is the via stub, the extension of a conductive via beyond the trace connection at a given backplane layer, as shown at 127. Although back-drilling may be used to remove the offending metal, such operations tend to be expensive and time consuming as the drilling depth varies from via to via according to the trace contact point and requires precise control to avoid destroying the via-to-trace junction.
Another bandwidth-limiting phenomenon is signal loss in the conductive traces 113, 117 disposed on the substrate layers of the backplane 101 and PCBs 119. Total signal loss is the result of conductor loss and dielectric loss and therefore depends both on the thickness and width of the signal traces and the dielectric properties of the substrate material. Moreover, control of the width of the signal traces is critical to performance lest more discontinuities be introduced. The thickness and width of the signal traces are normally limited due to manufacturing and design constraints and the substrate materials that are easiest to manufacture with are not always the ones with the best dielectric properties for high speed signal transmission.
Crosstalk is another source of noise in the interconnection system 100 and results from inductive or capacitive coupling of signals propagating on neighboring traces and other signal path elements. Crosstalk increases as the various backplane traces 113, PCB traces 117, and connector contacts become more densely routed, and typically limits the total number of signal paths that can be supported by the interconnection system 100 at a given operating frequency.
Timing skew is another phenomenon that can affect signal bandwidth in the interconnection system 100 and results from unequal propagation times on different signal paths. Timing skew is particularly problematic in differential signaling systems, as non-simultaneous arrival of differential signals distorts the differential relationship, potentially causing reception errors. Consequently, significant time and effort are typically expended to establish equal-length differential signaling paths, such efforts often necessitating additional substrate layers in the backplane 101.